The present invention relates to a method of reading data on a recording medium, and more specifically to a method of reading data using a self-optimizing waveform equalizer.
As shown in FIG. 1, a head unit 12 reads data stored on a recording medium 11, such as an optical disk, magneto-optical disk, or magnetic disk, and outputs a read signal RD having a voltage corresponding to the state of the data ("1" or "0") to a data reader 13.
The data reader 13 includes a prefilter 14, an automatic gain control amplifier (AGC) 15, an A/D converter (ADC) 16, a waveform equalizer 17, and a PLL circuit 18. The prefilter 14 filters the read signal RD to output a signal having a desired frequency to the AGC 15. The AGC 15 amplifies the output signal from the prefilter 14 to output a signal having a predetermined amplitude. The ADC 16 converts the output signal from the AGC 15 into a digital signal and outputs the digital signal to the waveform equalizer 17.
The waveform equalizer 17 executes waveform shaping of the digital signal by means of an intensity (sensitivity) parameter set in advance, and outputs the waveform-shaped digital signal to a CPU 19 and PLL circuit 18 as a reproduced signal Dout. The CPU 19 generates read-out data consisting of a predetermined number of bits on the basis of the reproduced signal Dout from the waveform equalizer 17. The waveform equalizer 17 includes coefficients used during the waveform shaping.
The PLL 18 generates a clock signal CLK synchronized with the reproduced signal Dout and delivers the clock signal CLK to the ADC 16 and the waveform equalizer 17. The clock signal CLK is used in setting the timing for taking in the data "1" or "0". That is, the ADC 16 samples the signal from the AGC 15 synchronously with the input clock signal CLK, converts the sampled signal into a digital signal, and outputs the digital signal. The waveform equalizer 17 executes an operation synchronously with the input clock signal CLK. The PLL 18 possesses coefficients for synchronizing the clock signal CLK with the read signal RD.
As shown in FIG. 2, a sector of the recording medium 11 includes a preamble (PR) region 21, a training (TR) region 22, a sink byte (SB) region 23, and a data region 24.
The PR region 21 contains a preamble (PR) code used to synchronize the clock signal CLK from the PLL circuit 18 with the read signal RD. The bits of the PR code may all be "1", for example, and the read signal RD of the PR code may be a sine wave.
The TR region 22 contains a training (TR) code used to optimize the performance of the waveform equalizer 17. The TR code is bit data, for example, "001100111", and contains high frequency components and low frequency components as an analog signal.
The SB region 23 contains a sink byte (SB) code used to detect the start of the data region 24. The CPU 19 treats bit data following the SB code as record data and performs a process to the record data.
The PLL circuit 18 synchronizes the clock signal CLK with the read signal RD using the output signal from the waveform equalizer 17. The waveform equalizer 17 optimizes its coefficients, even when the PLL circuit 18 is in operation. When the output signal Dout input to the PLL circuit 18 varies, the PLL circuit 18 alters the frequency of the clock signal CLK. At this time, there is a possibility that the PLL circuit 18 cannot converge the coefficients while the PR code is being read. That is, the PLL circuit 18 may not be able to synchronize the clock signal CLK with the read signal RD. Also, the waveform equalizer 17 may not be able to optimize its coefficients by some chance, while the TR code is being read out. This makes it difficult to read data from the recording medium 11 or increase the read-out time. Such problem have been an obstacle preventing increasing the speed of data processing, the recording density of the recording medium 11, and the rotation speed (high speed read-out) of the recording medium.
It is therefore an object of the present invention to provide an improved method of reading data stored on a recording medium.